This invention relates to a method for removing unnecessary pessimism from static timing analyses. Specifically, for designs having combinational logic circuits fed by multiple registers, the present invention reduces the number and size of tags, which are node identifiers with a list of arrival times and partial path completion information, needed during static timing analysis.
In digital circuits, when a clock latches a first data value at a launch register or launch flip-flop, the clock must also arrive at a capture register or flip-flop which will store a second data value that is produced based on the first data value by combinational logic circuitry interposed between the launch register and the capture register. To ensure proper functionality of the capture register, the second data value produced by the combinational logic circuitry must arrive at the capture register before the next cycle of the clock arrives at the capture register. The interval during which the second data value is present at the capture register before the arrival of the next clock cycle is referred to as the setup time.
The second data value must also be maintained at the capture register for an interval after the arrival of the next clock cycle to ensure that the second data value is sampled properly. This interval specifying the amount of time required for the second data value to be sampled properly is referred to as the hold time.
In timing analysis, some circuits may be too slow and the setup time may fall below a required threshold duration. For example, the second data value may arrive at the capture register after the next clock cycle arrives resulting in a failure to capture the second data value at the next clock cycle. Some circuits may be too fast and the hold time may fall between a required threshold duration. For example, the second data value may arrive at the capture register before the next clock cycle arrives, but results in an inaccurate or incomplete capture of the second data value if the second data value is not held for long enough after the arrival of said next clock cycle.
Clock reconvergence pessimism may refer to timing slack that is introduced or maintained in the circuit to ensure that adequate setup and hold times are maintained. In conventional timing analysis tools, a breadth-first approach is used when maintaining tags for data arrival and data departure times at different nodes in a circuit design. Consequently, for a given node, all of the worst-case arrival times for inputs from the fan-in to a given node are maintained in the tag or node identifier. Breadth-first approaches improve run-time by not tracing each path from potential launch registers to potential capture registers, at the expense of increased tag sizes for the nodes, as all of the worst-case arrival times from the fan-in to a node are maintained. As the number of nodes increases, the size of the tags used by conventional timing analysis tools may increase exponentially.
Conventional approaches to static timing analysis may result in designs overly pessimistic setup and hold timing slack. Overly pessimistic timing slack may cause false failures that are then corrected by unnecessarily adding routing, which consumes short wire interconnect resources and affects the maximum operating frequency (Fmax) of the design.
It would therefore be desirable to improve the tag allocation used by static timing analysis tools.